The present invention relates generally to semiconductor chips, and, more particularly, to a semiconductor chip having a low-noise power supply arrangement.
In general, semiconductor chips are typically supplied with a power supply voltage (e.g., Vcc) and a reference (e.g., ground or Vss) voltage over separate lines, and typically incorporate an internal power supply generator coupled between the separate power supply voltage and reference voltage lines for generating an intermediate voltage having a level between that of the power supply and reference voltages (e.g., 1/2 Vcc).
Semiconductor memory devices, such as dynamic random access memories (DRAMs), include a memory array region and a peripheral circuit region formed on a single semiconductor chip. Inevitably, the intrinsic coupling capacitance between the power supply voltage and reference voltage lines thereof results in the transfer of unwanted noise from the reference voltage line to the power supply voltage line. This unwanted noise can seriously interfere with the normal operation of the memory device, and, in particular, can cause erroneous read/write of data from/into the memory array. This noise transfer problem has become more acute as the length of the power supply and reference voltage lines has increased, in parallel with increases in the integration density and storage capacity of semiconductor memory devices.
At present, the prevalent technique for reducing noise transfer between the power supply voltage and reference voltage lines is to provide a noise reduction capacitor coupled between the power supply voltage and reference voltage lines. FIGS. 1A and 1B are equivalent circuit diagrams which illustrate the use of a noise reduction capacitor in a peripheral circuit and a data output circuit of a semiconductor memory device, respectively. As can be seen in FIG. 1A, a noise reduction capacitor Cp is connected between a peripheral circuit power supply voltage line Vccp and a peripheral circuit ground voltage line Vssp. Similarly, as can be seen in FIG. 1B, a noise reduction capacitor Cq is connected between a data output circuit power supply voltage line Vccq and a data output circuit ground voltage line Vssq. In practice, such noise reduction capacitors Cp and Cq have only proven to be partially effective. More particularly, although such noise reduction capacitors Cp and Cq have reduced the noise transfer between the power supply voltage and ground voltage lines, there still exists a serious problem of noise transfer due to the below-described noise coupling phenomenon,
More particularly, when low logic level data is read from the memory array immediately after high logic level data has been read from the memory array, the data output line, which is driven by the data output buffer, is abruptly driven from a high voltage level to ground level, thereby causing a current spike to be generated on the ground voltage line Vssq (due to the rapid voltage swing). This current spike is then transferred to the power supply voltage line of the data output circuit via the coupling capacitor Cq, thereby introducing unwanted noise, which can result in a data output error. A similar problem exists with respect to the peripheral circuits of the semiconductor memory device, e.g., with respect to the sense amplifiers and associated bit lines of the memory device. Moreover, a noise component in the power supply voltage can be transferred from the power supply voltage line to the ground voltage line via the coupling capacitor Cq (or Cp).
Based on the above, it can be appreciated that there presently exists a need in the art for a power supply arrangement for a semiconductor chip which eliminates the above-described drawbacks and shortcomings of the presently available semiconductor chips.